1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to photomasks used during optical lithography and a method for fabricating the same.
2. Description of Related Art
The fabrication of an integrated circuit involves numerous processing steps. After impurity regions are formed within a semiconductor substrate and gate conductors/electrodes are defined upon the substrate, interconnect routing is placed across the substrate and connected to the impurity regions. An interlevel dielectric is formed between the interconnect routing and the substrate to isolate the two levels. Contact openings are formed through the dielectric and filled with a conductive material to electrically link the interconnect routing to select impurity regions in the substrate. Additional levels of interconnect routing separated by interlevel dielectric layers can be formed if desired. Different levels of the interconnect routing can be coupled together with ohmic contacts formed through the dielectric layers. Forming a multi-level integrated circuit in this manner reduces the overall lateral area occupied by the circuit.
Various features of the integrated circuit are typically defined using a technique known as optical lithography or photolithography. In optical lithography, a photosensitive film, i.e., photoresist, is spin-deposited across a substrate (e.g., a wafer) in which features are to be formed. An optical image is transferred to the photoresist by projecting a form of radiation, typically ultraviolet light, through the transparent portions of a photomask. A photochemical reaction alters the solubility of the regions of the photoresist exposed to the radiation. The photoresist is washed with a solvent known as a developer to preferentially remove the regions of higher solubility, followed by curing the remaining regions of the photoresist. The portions of the layer below the photoresist which are no longer covered by the photoresist are etched away to define features of the ensuing integrated circuit. The photoresist provides protection for the portions of the layer directly beneath the photoresist from being removed.
Unfortunately, as shown in FIGS. 1A and 1B, line end shortening is a phenomenon that often occurs during optical lithography. FIG. 1A depicts a maskplate or photomask having patterned rectangular opaque elements 10. The photomask is used to define a corresponding set of lines or features 12 on a semiconductor substrate, as shown in FIG. 1B. However, due to optical proximity effects, the lengths of features 12 are reduced in comparison to the lengths of the corresponding elements 10 on the maskplate (dashed lines 14 indicate the desired locations for the edges of features 12). This phenomenon is referred to as line end shortening. Such optical proximity effects can occur as a result of the diffraction of the radiation by small features. The scattering of the radiation adversely affects the resolution of the optical system such that the resulting photoresist features are skewed. The magnitude of these proximity effects is dependent upon the spacing between adjacent features. As such, optical proximity effects are particularly a problem during the fabrication of an isolated deep sub-micron feature of an integrated circuit.
Line end shortening can have a detrimental impact on the operation of the integrated circuit. As a result of line end shortening, the overlap of two structures, e.g., an active area to an overlying gate electrode, may be reduced, resulting in device leakage. Further, the overlapping area of a gate conductor to an overlying contact may be reduced, thereby undesirably causing an increase in contact resistance.
FIGS. 2A–2C illustrate the effect of line end shortening. FIG. 2A depicts a photomask used to pattern a feature of the semiconductor topography shown in FIG. 2B or 2c. The photomask shown in FIG. 2A includes a transparent substrate 16 upon which a non-transparent (opaque) patterned element 18 is formed. FIG. 2B depicts a semiconductor topography in which a metal contact 26 extends vertically through an interlevel dielectric 24 down to an impurity region 22 of a semiconductor substrate 20. A metal conductor 28 has been patterned on interlevel dielectric 24 and contact 26 using the photomask in FIG. 2A. Optical proximity effects have caused conductor 28 to be shorter in length than photomask feature 18 (indicated by dashed line 30). Consequently, the overlapping area between contact 26 and conductor 28 is significantly reduced, resulting in an increased contact resistance. FIG. 2c depicts another semiconductor topography in which an electrode 21 has been patterned on an active region 23 to form an active device known as a field-effect transistor (FET). The shortening of the extension of the electrode (indicated by dashed line 25) to the active area may cause electrical leakage in the device.
Line end shortening, therefore, may undesirably effect the operation of an integrated circuit. Accordingly, it would be desirable to provide a photomask suitable for patterning the features of an integrated circuit in accordance with their design specifications while simultaneously limiting line end shortening.